The TU Kaiserslautern is a medium sized technical university in Germany with approximately 14.000 students and about 170 full professors. The Chair of Microelectronic Systems Design, led by Prof. Norbert Wehn, is associated with the department of Electrical and Computer Engineering and has many years of experience in the fields of efficient architectures and implementations of digital baseband signal processing components with a strong focus on channel decoding under latency, throughput and energy constraints. Over the years, the research group has published more than 100 papers in this area. In particular, soft decoding methods for Turbo, LDPC and Polar codes are scientifically investigated. In these investigations, the close interaction between code, decoding algorithm and efficient hardware implementation is in the foreground. Both ASIC implementations in advanced technology nodes and FPGA implementations are considered. The chair has published numerous decoder implementations, which at the time of publication were the most efficient implementations with the highest throughput to date. Furthermore, the chair has been dealing with the efficient implementation of Neural Networks for many years, in particular LSTMs, which are much less researched than CNNs. Here, too, the focus is on the close interaction between the algorithm and efficient implementation. Further research topics are customized high-performance computing architectures on FPGAs across various application areas such as option price calculation, morphological image processing and finding of similarities in large graphs. Further research concerns low power techniques and the reliability in embedded systems, 3D integration and advanced memory architectures.
In the FunKI project, the TU Kaiserslautern will investigate NN-based transceivers and transceiver components with regards to their efficient implementation on advanced ASIC technologies and FPGAs. In particular, the trade-off between communications performance, corresponding algorithms and implementation efficiency plays a central role. To this end, different NN-based processing engines, specialized for various tasks in the baseband processing chain will be implemented and fully characterized as virtual silicon prototypes. In this way, bottlenecks for the implementation can be quickly identified. These insights are then fed back into the development of algorithms, allowing for an efficient partitioning of the baseband processing chain into NN-based and conventional processing components.
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